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Silicon Labs /Series0 /EZR32HG /EZR32HG320F64R68 /CMU /HFPERCLKEN0

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Interpret as HFPERCLKEN0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIMER0)TIMER0 0 (TIMER1)TIMER1 0 (TIMER2)TIMER2 0 (USART0)USART0 0 (USARTRF1)USARTRF1 0 (PRS)PRS 0 (IDAC0)IDAC0 0 (GPIO)GPIO 0 (VCMP)VCMP 0 (ADC0)ADC0 0 (I2C0)I2C0

Description

High Frequency Peripheral Clock Enable Register 0

Fields

TIMER0

Timer 0 Clock Enable
TIMER1

Timer 1 Clock Enable
TIMER2

Timer 2 Clock Enable
USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable
USARTRF1

Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable
PRS

Peripheral Reflex System Clock Enable
IDAC0

Current Digital to Analog Converter 0 Clock Enable
GPIO

General purpose Input/Output Clock Enable
VCMP

Voltage Comparator Clock Enable
ADC0

Analog to Digital Converter 0 Clock Enable
I2C0

I2C 0 Clock Enable

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data